Google is expanding its eighth-generation TPU portfolio with two new offerings, the TPU 8tx and the TPU 8i Max. This marks the first time Google has introduced four distinct system configurations in a single year, though it is not four new chip designs. The 8tx builds on existing silicon for confidential computing, marking a notable win for AMD, while the 8i Max combines two 8i chips into one package to tackle massive context windows.
Google TPU 8x
When we covered the TPU v8s at Hot Chips 2026, we highlighted how Google specialized networking for different workloads. The inference-focused TPU 8i uses a Boardfly topology with a maximum network-hop diameter of seven, compared to sixteen hops in the training-oriented torus design. This structural difference reduces latency for real-time reasoning, helping explain why Google continues to tailor interconnects rather than rely on a single fabric.
The TPU 8tx is the third system in the generation and targets regulated enterprises and governments running frontier or proprietary models alongside sensitive data. It uses the same silicon as the training-focused TPU 8t, but Google has paired it with custom 5th Gen AMD EPYC “Turin” hosts to build security directly into the hardware layer. Normally, data is encrypted at rest and in transit but must be unlocked in memory while a computer processes it. The 8tx keeps that active data protected through confidential computing, which encrypts data in use inside an isolated trusted execution environment.
Here is Google’s rendering of the TPU 8tx board. The illustration shows four accelerator chips with heat sinks and connector ports along one edge, giving a sense of the tray layout that pairs these accelerators with their Turin host CPUs.
For the 8tx host CPU, Google selected 5th Gen AMD EPYC Turin to match the TPU 8t’s PCIe Gen5 x16 interface. A dual-socket Turin configuration provides 128 Gen5 lanes, ensuring zero I/O oversubscription across four TPUs and high-speed NICs. Google noted that a Gen6 host like AMD EPYC Venice (stay tuned for more on that) would step down to Gen5 speeds without adding accelerator bandwidth, aligning with their 2027 hardware qualification schedule.
The 8tx also adopts the Boardfly network from the inference-oriented TPU 8i rather than the training-optimized torus. That topology reduces the maximum hops between chips, which matters for multi-step agents that make many sequential inference calls. Google claims up to 2x lower latency than TPU 8t with a near-zero performance penalty.
Google TPU 8i Max Packs Two Chips and More Memory
The fourth system, TPU 8i Max, attacks the memory wall from a different angle. When many agents work across an entire codebase or hours of video simultaneously, memory bandwidth becomes the bottleneck before compute does. Google combined two low-latency TPU 8i chips into a single multi-chip package.
That gives the 8i Max double the compute, double the SRAM, and double the HBM bandwidth of a single TPU 8i. Specifically, it offers 384 GB of high-bandwidth memory, about a third more than the TPU 8i, while HBM bandwidth doubles to 17.2TB/s and on-chip SRAM doubles to 768 MB. The TPU 8i Max doubles HBM bandwidth to 17.2 TB/s and on-chip SRAM to 768 MB, directly addressing the memory wall that bottlenecks large-context agentic workloads.
We asked and Google told us that if data must remain within the confidential computing domain, users should stick with TPU 8tx for inference and serving. This system retains the same low-latency Boardfly topology optimized for real-time tasks.
Final Words
Probably the key message here is that Google is tailoring its TPU offerings for different parts of the AI stack, and really even different customers. The TPU 8tx seems to be more of a customized product for confidential computing, while the TPU 8i Max is designed for inference. For AMD, this is probably not going to drive a 10% server CPU market share gain overnight. Instead, it is a big win because AMD is notching both a win for EPYC in a non-AMD accelerator system, and it is showing its confidential computing chops by winning a socket at a major hyperscaler.
