The Arm Neoverse S3 is the series of IP that underpins the company’s new Neoverse CSS offerings. Called the S3 Chassis, this is the IP that provides features like the interconnect between the cores so that Arm can deliver standardized blocks for its customers to use.
Arm Neoverse S3 Detailed for the Infrastructure Chiplet Era
An easy way to think of this, using the diagram is that the CPU block is the Arm Neoverse N3 or V3 core. The S3 chassis is the interconnect, NOC, MMU and so forth to help go from core to a larger IP block. The Neoverse CSS is selling everything together. While we often focus on the Neoverse V3 and N3 cores, CSS is a broader set of IP so customers expect that the cores can talk to other parts of the system with CSS, that is why the S3 chassis is needed.
There are three main components to the Arm Neoverse S3: CMN S3, MMU S3, and NOC S3. The CMN S3 is the interconnect that ties things like the cores, the system cache (often L3), the memory controllers, PCIe Gen6 and CXL 3.0 together. It is a bit interesting that Arm is using CXL 3.0 versus CXL 3.1 in its diagram. The CMN S3 is what also provides connectivity to other chiplets whether those are CPU chiplets, AI accelerator chiplets, or other chiplets on a package.
The NoC S3 is designed to help CSS designs connect to I/O coherent chiplets. On the memory management side, the MMU S3 is an important piece of IP since it helps ensure that, in larger topologies, that only the right memory is being accessed. In the future, especially with CXL 3.0/3.1, that is going to be a big deal.
Final Words
Overall, it is probably one of the more overlooked aspects of the Neoverse platform, but when we speak to folks in the industry for big chips, chiplets are the way forward, perhaps with some smaller volume designs for specific applications. As a result, the Neoverse S3 is an important building block for those building custom CPUs.
