The AMD EPYC 9004X parts, codenamed “Genoa-X” are a continuation of a line launched with the previous generation of processors. AMD takes its fast server processors and adds another layer of cache to the CCDs for massive caches. In this context, 1.1GB+ of cache.
We are writing these live during the AMD Data Center 2023 event, so please excuse the typos.
AMD Genoa-X The 1.1GB L3 Cache CPU Launched
Genoa-X takes the 3D V-Cache stacking we saw with Milan-X and brings it to the Genoa generation. These are chips designed for HPC applications. Often, having more on-chip cache means that cores are spending less time waiting for memory access to RAM. Modern CPU cores are so fast, feeding them with data is a major challenge. More cache means more data is stored in cache and therefore higher cache hits. Each cache hit that avoids DDR5 DIMM access means higher performance at lower power consumption.
This is one where we are actually going to go into a bit less detail. For STH readers, we have more on 3D V-Cache details in our AMD Milan-X Delivers AMD EPYC Caches to the GB-era deep dive. The biggest difference is that this is AMD EPYC Genoa as the base CPU, not Milan.
Feel free to check out the video if you prefer on Milan-X to understand how this works, and where performance increases.
Final Words
This is probably not going to be the highest-volume product for AMD that will be announced today. Microsoft Azure will use the part, especially for its HPC instances because of the awesome performance they saw with 3D V-Cache.
What this shows is that AMD is continuing its portfolio of focused CPU solutions for different tasks. This is the HPC part, whereas Bergamo is the cloud scale-out part, and Genoa is the general-purpose CPU. For higher-end HPC, AMD has the AMD Instinct MI300 platform for CPU and GPU compute.
Can’t for RAM-less EPYC processor