AMD EPYC 9006 Results Are Here and AMD Delivers a Knockout Part Deux

At long last, the day is here. Today, we finally get to share with you our first look at AMD’s EPYC “Venice” series, or the EPYC 9006 processors.

Following AMD’s biennial CPU development roadmap, the highlight of the year for AMD’s CPU teams is the launch of the EPYC 9006 processors and the Zen 6 CPU architecture that underlies them. Admidst an unprecidented explosing in demand for server CPUs for AI systems to drive both host nodes and agnetic workloads, AMD finds itself in a very commanding position, bringing to market a new generation of even more powerful server hardware right when the industry seems to need it most. All the while, AMD has ambitions of becoming the undisputed market leader for server CPUs – ambitions that Venice seems primed to help AMD reach.

As far as server CPU launches go, today’s launch is remarkable on multiple levels. Besides taking a look at a wholly new server platform from AMD (socket and all), which would normally be a big event in and of itself, the server boom has turned the CPU development cycle on its head, and now it is a server CPU where we will see AMD’s latest CPU architecture. So along with our first benchmarks of Venice, today also marks our first chance to evaluate the Zen 6 CPU architecture that will be driving so many AMD products over the coming two years – everything ranging from server chips like Venice and Verano to consumer desktops, laptops, and more. There is a lot to unpack with today’s launch.

With so much to do and so little time to do it all, we are going to have a lot more content to follow. But to get things started, for today’s launch piece we are going to run the flagship EPYC 9996 through not only our agentic-workload focused AgentSTH V7 benchmark suite, but we are also including bits and pieces of what is essentially a preview of 2027’s AgentSTH V8. For some context, we are going back roughly a decade in server architectures to not just blindly pick up benchmark suites, but to profile workloads on dozens of platforms for inclusion in the suite.

We have lots of numbers for this one and some neat comparison points. The headline feature is that we now get up to 256 cores per socket, a new PCIe Gen6 I/O subsystem, and more than twice the memory bandwidth to go along with a revised Zen 6 microarchitecture and SoC design. AMD is also splitting its lineup into multiple families for different applications with two primary sockets, a return of the -X high-cache parts with Venice-X, and the LPDDR5X Verano. The new series covers a lot more and is by far the most ambitious innovation in the EPYC line since the switch to an I/O die, which allowed the EPYC 7002 to deliver a knockout. This is the Knockout Part Deux.

Also, I just wanted to recognize Ryan, Sam, and Vic for contributing to a quick turnaround on this one. We will have Ryan cover the Zen 6 microarchitecture and SoC portion before I take back over on performance. Regular STH readers may have noticed this, but many of our pieces are much longer than they used to be, and doing these reviews has become a team effort.

AMD EPYC 9006 “Venice”: The Story So Far

Over the summer, AMD held a proper unveiling for its EPYC 9006 “Venice” server CPU platform at the company’s annual Advancing AI event. In what has become AMD’s marquee event of the year – and a reflection of the importance of server parts to their bottom line – the company laid out an aggressive plan for 2026 and beyond. Spearheaded by the Venice CPU platform, AMD has ambitions to deliver not only their most powerful and most capable server platform to date, but to iterate on that over the next year or so to deliver a broad portfolio of server chips that covers everything from rank-and-file servers to mighty HPC systems, and of course lots of AI nodes.

Now in its sixth generation of Zen-architecture server chips, Venice is in some respects AMD’s most aggressive design yet. AMD is making heavier use of chiplets than ever before, and the company is now relying on advanced packaging techniques to tie them all together. This has allowed AMD to fully leverage TSMC’s N2 (2nm) process node, their first GAAFET-based node, to the best of their abilities, tapping it to not only devote more transistors than ever to the Zen CPU cores to boost their performance, but to pack in more CPU cores than ever before.

For high-throughput workloads, the highlight of Venice is that there are now up to 256 CPU cores in a single socket, a 33% improvement over EPYC 9005 “Turin” only a generation ago – and with 20% higher IPC and higher clockspeeds on top of that. Meanwhile for workloads where single-threaded performance and latency are more critical, AMD is bringing the 5.3GHz EPYC 9686F to market to double-down on Zen 6’s IPC improvements with the highest clockspeeds yet for an EPYC server chip.

AMD is keen to tap into the agentic era of computing. And there are a lot of improvements to Venice and the Zen 6 CPU architecture that are going to help them get there. But do not underestimate the chip in other areas, either; AMD has invested in features such as PCIe Gen6, new virtualization and security features, and it has even picked up a software engineering firm in recent months to develop software to replace DRAM with flash memory. AI is certainly the highlight of the Venice story, but it is not the only story.

With any luck, AMD expects that over the next 12 months they will finally reach the point where they capture leadership of the server CPU market. As we saw with AMD’s earnings last week, the company’s data center division is already projecting that its revenues will surpass Intel’s in Q4 of this year. Meanwhile, AMD is already at 46% of the revenue share for the x86 server CPU market, and the company seems confident that Venice will help push them above 50% for the very first time.

EPYC 9006 SP7 Product Stack: Venice HF Gets a Spec Bump

Alongside its initial summer announcement of the EPYC 9006 lineup, AMD also published the complete specifications for its full stack of chip SKUs. This was for both the high-end SP7 platform launching today, as well as the more restrained SP8 platform that is launching early next year.

As it turns out, AMD was sandbagging things a bit. Whereas their flagship high-frequency chip, the EPYC 9686F, was originally announced to ship with a peak frequency of 5.0GHz, that is no longer the case.

Instead, the 9686F is now a 5.3GHz chip. Making this a notable improvement just ahead of the launch of the hardware, and admittedly a bit of a point of pride (or at least bragging rights) for AMD.

In talking with AMD, the company has found that the final silicon for their big Zen 6 CCD has turned out even better than the company was expecting. Consequently, their earlier SKU stack was a bit conservative, and they can do a bit better than 5.0GHz – and allow the fastest Venice to clock higher than the fastest Turin after all.

So here is what the final, shipping SP7 chip stack looks like.

Only the EPYC 9686F is getting a specification bump here. The rest of the lineup is unchanged from before. Notably, this means the 64 core EPYC 9586F does not get to share in the gains. So if customers want AMD’s highest clocked Venice chip, they will need to buy the 96 core version.