At Supercomputing 2020 (SC20) Intel is extolling the virtues of its upcoming Intel Xeon CPUs codenamed “Ice Lake”. Beyond the new CPUs, Intel is discussing how the next-generation Xeons will be part of the overall XPU strategy. Something that is notable is that the cover image above was of an Ice Lake Xeon when it was getting ready for release at Intel Architecture Day 2018. It is not clear that many in 2018 expected it to launch in 2021 to the point that we are only getting a few high-level slides two years later at SC20.
Intel Ice Lake Xeon at SC20
Kicking this off, Intel still sees the Xeon product line as the cornerstone of its XPU strategy. Intel has the Xe HPC GPU, FPGAs, and AI accelerators that it will use to augment traditional x86 compute.
At Intel Architecture Day 2020 we got more details about both Ice Lake Xeon and Sapphire Rapids. Intel is starting to discuss Sapphire Rapids more in its materials. As the roadmap stands, Ice Lake will be a shorter duration generation with a single chip in the Whitley platform. Sapphire Rapids has new extensions, new memory capabilities, and CXL/ PCIe Gen5. We discussed the 2021 Ice Pickle where Ice Lake is getting its time on the market compressed by Sapphire.
Still, Intel has its Ice Lake generation coming out in 2021. Early launch activities have already started before the public release. We get parity with modern Arm and AMD platforms with eight-channel DDR4, new microarchitecture, PCIe Gen4.
We will also get new security enhancements toward confidential computing goals. Intel Optane PMem 200 was launched with Cooper Lake with a catch. With Cooper Lake, it can only run as persistent storage, not in-memory mode. With Ice Lake, we will get memory mode with PMem 200.
We checked the performance footnotes. Intel is comparing a pre-production 32 core Ice Lake Xeon to AMD EPYC 7742 64-core part and seeing 20-30% performance uplift. This is impressive, but given AVX512 it is what we may expect here.
Of course, there are a few notes. First, the AMD EPYC 7742 is a 2019 part. AMD has been in volume production with the EPYC 7003 “Milan” series since September 2020 and has been shipping to major cloud providers. These are not ES shipments, these are full volume production. We will get the marketing release for non-HPC/ cloud customers but Milan is already out which makes this Intel comparing a pre-production 2021 part to a previous-generation AMD part.
In the performance footnotes, we did not get TDPs. The AMD EPYC 7742 has a 225W TDP but can handle up to 240W cTDP. We have brought up this fact to Intel previously. Indeed, at STH we recently tested the AMD EPYC 7H12 which is a HPC part with 280W TDP. We do not know the TDP of the Intel part. As a result, we do not know if Intel is comparing a relatively high power 32 core chip to a relatively low power 64 core part. Finally, Intel is using Intel MKL in these benchmarks which does not have the best history of being vendor-neutral in its implementation. Milan will have higher TDPs just like Ice Lake. Claiming a 20-30% performance uplift over older generation parts on HPC-specific workloads is not exactly a win given we have some sense of how Ice Lake will perform compared to EPYC in non-HPC workloads.
With a 18% uplift in IPC for SPECcpu2017 with Sunny Cove, we expect that for many of these non-HPC AVX-512 workloads Intel will need much higher performance to match AMD’s 64 core parts.
As with anything, we urge our readers to read vendor claims critically. Intel is touting customer wins for when the chips finally launch. The AMD EPYC 7742 is already in a number of systems on the November 2020 Top500 list. Our analysis piece is done, just awaiting a publishing slot.
Of course, the big excitement is with the Intel Xe architecture. Intel is saying that, although the Xe HPC is still a bit behind, the Xe HP parts are starting to be available to developers. We recently covered the Intel Server GPU based on Xe LP and designed for video transcoding rather than HPC compute.
Perhaps the bigger bet is still on oneAPI. Intel hopes to make the XPU development and utilization relatively seamless through software development. It is not lost that in some ways Intel may have a more modern software stack than hardware stack in 2020 when one API goes gold.
For us, oneAPI is more exciting than Ice Lake Xeons.
Final Words
Overall, this was a relatively meager SC20 disclosure from Intel. We get a few new details, but as Ice Lake Xeons are seeing release dates push back on a regular basis, they are competing with different generations of processors from Intel’s competition.
While we are not overly excited by the Intel 2020-2021 generation of hardware given these delays, oneAPI and XPU is a solid effort that will continue to pay dividends as we get to the 2022 and beyond generations. If you want to understand what is happening in 2021 in the Xeon portfolio, check out our Ice Pickle article linked above or the video version below.
Intel is not in good shape… tech tech potato is also not very optimistic on intels 10 nm (youtube). Meanwhile TSMC is delivering 5 nm. NVidia is trying to buy ARM. AMD is trying to buy Xilinx. Apple doesn’t need them anymore. It doesn’t look good… not for intel nor for the end user, who mostly benefits from competition.
Intel announced sampling of Ice Lake Server back in June 2019. Recently Intel announced that Ice Lake Server chips are in qualification. Oracle and others have already announced products.
Intel announced that Sapphire Rapids was in the lab back in August and, recently, that it is broadly sampling.
AMD’s announced in q2 cc that “We’re excited about Milan. Milan is looking good in the labs.”
So, what do we make of these announcements? Does Milan go straight from “in the labs” to products?
Intel has its work cut out for it if they think renaming OpenCL to OneAPI is going to make people use it. It’s tough enough to generate “code” for variable targets, but also hard to compete for specific use cases.
For a large fraction of numerics I am going to use the BLAS or something that uses the BLAS like numpy.
For neural networks what I use is going to have an automatic differentiator. I have “been there, done that” with hard coded vector instructions and helped make a great product, but no way we were going to: (i) change the network, training procedure, etc. or (ii) upgrade the code to the next generation of vector instructions. There has to be a high-level experience like PyTorch or Tensorflow or forget about it.
FGPA?
Is this the way the unique potential of the FPGA? Is it the revolution in FPGA tooling the industry needs? What is the spend really on FPGA when it is cost effective to make an ASIC for a high-end item (think sidewinder missile brain or cell phone base station) that is produced in four digits worth of units?
Most of the code I write is really branchy and I want either great single thread performance despite that or some end-run around it such as what this guy writes
https://lemire.me/blog/2020/10/20/ridiculously-fast-unicode-utf-8-validation/
E-commerce, banking, e-business involve a lot of parsing and unparsing JSON or XML or CSV. It is staggering how many FP64 operations you can do in the time it takes to parse a string to an FP64 and serialize it back.